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mma685x rev 1, 05/2010 freescale semiconductor technical data ? freescale semiconductor, in c., 2010. all rights reserved. single axis spi inertial sensor mma685x is a spi-based, single axis, medium-g, over-damped lateral accelerometer designed for us e in automotive airbag systems. features ? 20g to 120 g full-scale range ? 3.3 v or 5 v single supply operation ? spi-compatible serial interface ? 10-bit digital signed or unsigned spi data output ? programmable arming functions ? twelve low-pass filter options, ranging from 50 hz to 1000 hz ? optional offset cancellation with > 6s averaging period and < 0.25 lsb/s slew rate ? pb-free 16-pin qfn-6x6 package referenced documents ? aec-q100, revision g, dated may 14, 2007 ordering information device axis axis range shipping MMA6851QR2 x 25g tape & reel mma6852qr2 x 35g tape & reel mma6853qr2 x 50g tape & reel mma6854qr2 x 75g tape & reel mma6855qr2 x 120g tape & reel mma6856qr2 x 60g tape & reel mma685x single axis spi inertial sensor 16-pin qfn case 1477-02 pin connections bottom view top view v rega v ss n/c v ssa n/c v ssa test/v pp miso mosi sclk v cc v ss v reg arm/pcm 1 2 3 4 5 6 7 8 12 11 10 9 16 15 14 13 cs n/c 17
sensors 2 freescale semiconductor mma685x figure 1. application diagram device orientation figure 2. device orientation diagram table 1. external component recommendations ref des type description purpose c1 ceramic 0.1 f, 10%, 10 v minimum, x7r v cc power supply decoupling c2 ceramic 1 f, 10%, 10 v minimum, x7r voltage regulator output capacitor (c reg ) c3 ceramic 1 f, 10%, 10 v minimum, x7r voltage regulator output capacitor (c rega ) c3 c1 c2 v cc mma685x v cc v reg v rega v ss v pp /test cs sclk arm cs_a sclk1 mosi1 main mcu miso1 cs_d sclk2 mosi2 miso2 cs sclk mosi miso deployment ic deploy_en v ssa mosi miso x: 0g earth ground x: +1g x: 0g x: -1g x: 0g x: 0g xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx
sensors freescale semiconductor 3 mma685x internal block diagram figure 3. block diagram ? converter oscillator 8 mhz 1 mhz regulator digital x-axis g-cell over-damped sinc filter compensation low-pass filter cancellation offset arm_x v rega v reg monitoring clock v rega v reg v cc iir v pp v cc v reg v ss v rega v ssa arm cs sclk mosi miso odd register array generation clock crc i/o spi mismatch spi even register array verification clock & bias generator spi odd register spi even register otp array memory analog regulator self test voltage monitoring linear interpolation output scaling offset monitor
sensors 4 freescale semiconductor mma685x 1 pin connections figure 4. 16-pin qfn package, top view table 2. pin description pin pin name formal name definition 1 v rega analog supply this pin is connected to the power supply for the inte rnal analog circuitry. an external capacitor must be connected between this pin and v ssa . reference figure 1 . 2 v ss digital gnd this pin is the power supply retu rn node for the digital circuitry. 3 v reg digital supply this pin is connected to the power supply for the intern al digital circuitry. an external capacitor must be connected between this pin and v ss . reference figure 1 . 4 v ss digital gnd this pin is the power supply retu rn node for the digital circuitry. 5 n/c no connect no connection 6 arm/ pcm arm output / pcm output the function of this pin is configurable via the devcfg register as described in section 3.1.6.5 . when the arming output is selected, arm can be configured as an open drain, active low output with a pull-up current; or an open drain, active high output with a pull-down cu rrent. alternatively, this pin can be configured as a digital output with a pcm signal proportional to the acceleration data. reference section 3.8.9 and section 3.8.10 . if unused, this pin must be left unconnected. 7 test/ v pp programming voltage this pin provides the power for factory programming of the otp registers. this pin must be connected to v ss in the application. 8 miso spi data out this pin functions as the serial data output for the spi port. 9 v cc supply this pin supplies power to the device. an external capacitor must be connected between this pin and v ss . reference figure 1 . 10 sclk spi clock this input pin provides the serial cl ock to the spi port. an internal pull-do wn device is connected to this pin. 11 mosi spi data in this pin functions as the serial data input to the spi por t. an internal pull-down device is connected to this pin. 12 cs chip select this input pin provides the chip select for the spi por t. an internal pull-up device is connected to this pin. 13 v ssa analog gnd this pin is the power supply return node for analog circuitry. 14 n/c no connect no connection 15 n/c no connect no connection 16 v ssa analog gnd this pin is the power supply return node for analog circuitry. 17 pad die attach pad this pin is the die attach flag, and is internally connected to v ss . v rega v ss n/c v ssa n/c v ssa test/v pp miso mosi sclk v cc v ss v reg arm/pcm 1 2 3 4 5 6 7 8 12 11 10 9 16 15 14 13 cs n/c 17
sensors freescale semiconductor 5 mma685x 2 electrical characteristics 2.1 maximum ratings maximum ratings are the extreme limits to which the dev ice can be exposed without permanently damaging it. 2.2 operating range the operating ratings are the limits normally expected in the application and define the range of operation. # rating symbol value unit 1 supply voltage v cc -0.3 to +7.0 v (3) 2 c reg , c rega v reg -0.3 to +3.0 v (3) 3 sclk, cs , mosi,v pp /test v in -0.3 to v cc + 0.3 v (3) 4 arm v in -0.3 to v cc + 0.3 v (3) 5 miso (high impedance state) v in -0.3 to v cc + 0.3 v (3) 6 acceleration without hitting internal g-cell stops g gcell_clip 500 g (3, 18) 7 acceleration without saturation of internal circuitry g adc_clip 375 g (3) 8 powered shock (six sides, 0.5 ms duration) g pms 1500 g (5, 18) 9 unpowered shock (six sides, 0.5 ms duration) g shock 2000 g (5, 18) 10 drop shock (to concrete surface) h drop 1.2 m (5) 11 12 13 electrostatic discharge human body model (hbm) charge device model (cdm) machine model (mm) v esd v esd v esd 2000 750 200 v v v (5) (5) (5) 14 storage temperature range t stg -40 to +125 c (5) 15 thermal resistance - junction to case q jc 2.5 c/w (14) # characteristic symbol min typ max units 16 17 supply voltage standard operating voltage, 3.3 v standard operating voltage, 5.0 v v cc v l +3.135 v typ +3.3 +5.0 v h +5.25 v v (15) (15) 18 operating ambient temperature range verified by 100% final test t a t l -40 ? t h +105 c (1) 20 power-on ramp rate (v cc )v cc_r 0.000033 ? 3300 v/ s (19)
sensors 6 freescale semiconductor mma685x 2.3 electrical characterist ics - power supply and i/o v l (v cc - v ss ) v h , t l t a t h , | t a | < 25 k/min unless otherwise specified # characteristic symbol min typ max units 21 supply current * i dd 3.0 ? 7.0 ma (1) 22 23 24 25 26 27 28 29 power supply monitor thresholds (see figure 8 ) v cc under voltage (falling) v reg under voltage (falling) v reg over voltage (rising) v rega under voltage (falling) v rega over voltage (rising) power supply monitor hysteresis v cc under voltage (falling) v reg under voltage, v reg over voltage v rega under voltage, v rega over voltage * * * * * v cc_uv_f v reg_uv_f v reg_ov_r v rega_uv_f v rega_ov_r v hyst v hyst v hyst 2.74 2.10 2.65 2.20 2.65 65 20 20 ? ? ? ? ? 100 100 100 3.02 2.25 2.85 2.35 2.85 110 210 150 v v v v v mv mv mv (3, 6) (3, 6) (3, 6) (3, 6) (3, 6) (3) (3) (3) 30 31 32 power supply reset thresholds (see figure 5 , and figure 8 ) v reg under voltage reset (falling) v reg under voltage reset (rising) v reg reset hysteresis * * v reg_uvr_f v reg_uvr_r v hyst 1.764 1.876 80 ? ? ? 2.024 2.152 140 v v mv (3, 6) (3, 6) (3) 33 34 internally regulated voltages v reg v rega * * v reg v rega 2.42 2.42 2.50 2.50 2.58 2.58 v v (1, 3) (1, 3) 35 36 external filter capacitor (c reg , c rega ) value esr (including interconnect resistance) c reg esr 700 ? 1000 ? 1500 400 nf m (19) (19) 37 38 power supply coupling 50 khz f n 300 khz 4 mhz f n 100 mhz ? ? ? ? 0.004 0.004 lsb/mv lsb/mv (19) (19) 39 40 output high voltage (miso, pcm) 3.15 v (v cc - v ss ) 3.45 v (i load = -1 ma) 4.75 v (v cc - v ss ) 5.25 v (i load = -1 ma) * * v oh_3 v oh_5 v cc - 0.2 v cc - 0.4 ? ? ? ? v v (2, 3) (2, 3) 41 42 output low voltage (miso , pcm) 3.15 v (v cc - v ss ) 3.45 v (i load = 1 ma) 4.75 v (v cc - v ss ) 5.25 v (i load = 1 ma) * * v ol_3 v ol_5 ? ? ? ? 0.2 0.4 v v (2, 3) (2, 3) 43 44 open drain output high voltage (arm) 3.15 v (v cc - v ss ) 3.45 v (i arm = -1 ma) 4.75 v (v cc - v ss ) 5.25 v (i arm = -1 ma) * * v odh_3 v odh_5 v cc - 0.2 v cc - 0.4 ? ? ? ? v v (2, 3) (2, 3) 45 46 open drain output pull-down current (arm) 3.15 v (v cc - v ss ) 3.45 v (v arm = 1.5 v) 4.75 v (v cc - v ss ) 5.25 v (v arm = 1.5 v) * * i odpd_3 i odpd_5 50 50 ? ? 100 100 a a (2, 3) (2, 3) 47 48 open drain output low voltage (arm) 3.15 v (v cc - v ss ) 3.45 v (i arm = 1 ma) 4.75 v (v cc - v ss ) 5.25 v (i arm = 1 ma) * * v odh_3 v odh_5 ? ? ? ? 0.2 0.4 v v (2, 3) (2, 3) 49 50 open drain output pull-up current (arm) 3.15 v (v cc - v ss ) 3.45 v (v arm = 1.5 v) 4.75 v (v cc - v ss ) 5.25 v (v arm = 1.5 v) * * i odpu_3 i odpu_5 -100 -100 ? ? -50 -50 a a (2, 3) (2, 3) 51 input high voltage cs , sclk, mosi, miso * v ih 1.7 ?? v(3, 6) 52 input low voltage cs , sclk, mosi, miso * v il ?? 1.0 v (3, 6) 53 input voltage hysteresis cs , sclk, mosi, miso * v i_hyst 0.125 ? 0.500 v (19) 54 55 input current high (at v ih ) (sclk, mosi) low (at v il ) (cs ) * * i ih i il -260 30 -50 50 -30 260 a a (2, 3) (2, 3)
sensors freescale semiconductor 7 mma685x 2.4 electrical characteristi cs - sensor and signal chain v l (v cc - v ss ) v h , t l t a t h , | t a | < 25 k/min unless otherwise specified # characteristic symbol min typ max units 56 57 58 59 60 61 digital sensitivity (spi, 10-bit output) 25g (MMA6851QR2) 35g (mma6852qr2) 50g (mma6853qr2) 60g (mma6856qr2) 75g (mma6854qr2) 120g (mma6855qr2) * * * * * * sens sens sens sens sens sens ? ? ? ? ? ? 20.479 13.947 9.766 8.192 6.510 4.096 ? ? ? ? ? ? lsb/g lsb/g lsb/g lsb/g lsb/g lsb/g (1, 9) (1, 9) (1, 9) (1, 9) (1, 9) (1, 9) 62 63 67 sensitivity error t a = 25c -40c t a 105c -40c t a 105c,v cc_uv_f v cc - v ss v l * * sens sens sens -4 -5 -5 ? ? ? +4 +5 +5 % % % (1) (1) (3) 68 69 70 71 offset at 0g (no offset cancellation) 10-bits, unsigned 10-bits, signed 10-bits, unsigned, v cc_uv_f v cc - v ss v l 10-bits, signed, v cc_uv_f v cc - v ss v l * * offset offset offset offset 482 -30 482 -30 512 0 ? ? 542 +30 542 +30 lsb lsb lsb lsb (1) (1) (3) (3) 72 73 offset monitor thresholds positive threshold (10-bits, unsigned) negative threshold (10-bits, unsigned) offthr pos offthr neg ? ? 564 460 ? ? lsb lsb (7) (7) 74 75 76 77 range of output (spi, 10-bits, unsigned) normal fault response code unused codes unused codes range fault unused unused 32 ? 1 993 ? 0 ? ? 992 ? 31 1023 lsb lsb lsb lsb (7) (7) (7) (7) 78 79 80 81 range of output (spi, 10-bits, signed) normal fault response code unused codes unused codes range fault unused unused -480 ? -511 481 ? -512 ? ? 480 ? -481 511 lsb lsb lsb lsb (7) (7) (7) (7) 82 nonlinearity * nl out -1 ? 1 % fsr (3) 83 84 system output noise rms (10-bit, all ranges, 400 hz, 4-pole lpf) peak to peak (10-bit, all ranges, 400 hz, 4-pole lpf) n rms n p-p ? ? ? ? 0.5 1.0 lsb lsb (3) (3) 85 86 cross-axis sensitivity v zx v yx * * v zx v yx -4 -4 ? ? +4 +4 % % (3) (3) 87 88 89 90 91 92 self-test output change (ref section 3.6 ) stmag = 0, t a = 25c stmag = 0, -40c t a 105c stmag = 1, t a = 25c stmag = 1, -40c t a 105c stmag = 0, -40c t a 105c v cc_uv_f v cc - v ss v l stmag = 1, -40c t a 105c v cc_uv_f v cc - v ss v l * * * * st low25 st low st hi25 st hi st low st hi st min 11.25 10.68 22.5 21.37 10.68 21.37 st nom 15 15 30 30 15 30 st max 18.75 19.69 37.5 39.38 19.69 39.38 g g g g g g (1) (1) (1) (1) (3) (3) 93 acceleration (without hitting internal g-cell stops) any range positive/negative g g-cell_clip 500 560 600 g (19)
sensors 8 freescale semiconductor mma685x 2.5 dynamic electrical char acteristics - signal chain v l (v cc - v ss ) v h , t l t a t h , | t a | < 25 k/min unless otherwise specified # characteristic symbol min typ max units 94 95 96 dsp sample rate (lpf 0,1,2,3,4,5) dsp sample rate (lpf 8,9,10,11,12,13) interpolation sample rate t s t s t interp ? ? ? 64/f osc 128/f osc t s /2 ? ? ? s s s (7) (7) (7) 97 98 datapath latency (excluding g-cell and low pass filter) t s = 64/f osc t s = 128/f osc * * t datapath_8 t datapath_16 33.0 51.9 34.8 54.6 36.5 57.4 s s (7, 16) (7, 16) 99 100 101 102 103 104 low-pass filter (t s = 8 s) cutoff frequency 0: 100 hz, 4-pole cutoff frequency 1: 300 hz, 4-pole cutoff frequency 2: 400 hz, 4-pole cutoff frequency 3: 800 hz, 4-pole cutoff frequency 4: 1000 hz, 4-pole cutoff frequency 5: 400 hz, 3-pole * * * * * * f c0(lpf) f c1(lpf) f c2(lpf) f c3(lpf) f c4(lpf) f c5(lpf) 95 285 380 760 950 380 100 300 400 800 1000 400 105 315 420 840 1050 420 hz hz hz hz hz hz (3, 7, 17) (7, 17) (7, 17) (7, 17) (7, 17) (7, 17) 105 106 107 108 109 110 low-pass filter (t s = 16 s) cutoff frequency 8: 50 hz, 4-pole cutoff frequency 9: 150 hz, 4-pole cutoff frequency 10: 200 hz, 4-pole cutoff frequency 11: 400 hz, 4-pole cutoff frequency 12: 500 hz, 4-pole cutoff frequency 13: 200 hz, 3-pole * * * * * * f c8(lpf) f c9(lpf) f c10(lpf) f c11(lpf) f c12(lpf) f c13(lpf) 47.5 142.5 190 380 475 190 50 150 200 400 500 200 52.5 157.5 210 420 525 210 hz hz hz hz hz hz (7, 17) (7, 17) (7, 17) (7, 17) (7, 17) (7, 17) 111 112 113 114 115 116 117 offset cancellation (normal mode, 10-bit output) offset averaging period offset slew rate offset update rate offset correction value per update positive offset correction value per update negative offset correction threshold positive offset correction threshold negative * * * * * * * off aveper off slew off rate off corrp off corrn off thp off thn ? ? ? ? ? ? ? 6.291456 0.2384 1049 0.25 -0.25 0.125 0.125 ? ? ? ? ? ? ? s lsb/s ms lsb lsb lsb lsb (7) (7) (7) (7) (7) (7) (7) 118 offset monitor bypass time after self-test deactivation t st_omb ? 320 ? t s (3, 7) 119 time between acceleration data requests t acc_req 15 ?? s (3, 7, 20) 120 121 122 arming output activation time (arm, i arm = 200 a) moving average and count arming modes (2,3,4,5) unfiltered mode activation delay (reference figure 28 ) unfiltered mode arm assertion time (reference figure 28 ) t arm t arm_uf_dly t arm_uf_assert 0 0 5.00 ? ? ? 1.05 1.05 6.579 s s s (3, 12) (3, 12) (3) 123 sensing element natural frequency (-40c t a 105c) f gcell 10791 13464 15879 hz (19) 124 sensing element cutoff frequency (-3 db ref. to 0 hz, -40c t a 105c) f gcell 0.851 1.58 2.29 khz (19) 125 sensing element damping ratio (-40c t a 105c) gcell 2.46 4.31 9.36 ? (19) 126 sensing element delay (@100 hz, -40c t a 105c) f gcell_delay 70 101 187 s (19) 127 package resonance frequency f package 100 ?? khz (19) 128 package quality factor q package 1 ? 5 (19)
sensors freescale semiconductor 9 mma685x 2.6 dynamic electrical char acteristics - supply and spi v l (v cc - v ss ) v h , t l t a t h , | t a | < 25 k/min unless otherwise specified 1. parameters tested 100% at final test. 2. parameters tested 100% at wafer probe. 3. parameters verified by characterization 4. (*) indicates a critical characteristic. 5. verified by qualification testing. 6. parameters verified by pass/fail testing in production. 7. functionality verified 100% via scan. timing characteristic is directly determined by internal oscillator frequency. 8. n/a 9. devices are trimmed at 100 hz with 1000 hz low-pass filter option selected. response is corrected to 0 hz response. 10. low-pass filter cutoff frequencies shown are -3db referenced to 0 hz response. 11. power supply ripple at frequencies greater than 900 khz should be minimized to t he greatest extent possible. 12. time from falling edge of cs to arm output valid. 13. n/a 14. thermal resistance between the die junction and the expo sed pad; cold plate is attached to the exposed pad. 15. device characterized at all values of v l & v h . production test is conducted at all typical voltages (v typ ) unless otherwise noted. 16. data path latency is the signal latency from g-cell to spi output disregarding filter group delays. 17. filter characteristics are specified independently, and do not include g-cell frequency response. 18. electrostatic deflection test completed during wafer probe. 19. verified by simulation. 20. acceleration data request timing constraint only applies for proper operation of the arming function. # characteristic symbol min typ max units 129 130 power-on recovery time (vcc = vccmin to first spi access) power-on recovery time (internal por to first spi access) t op t op ? ? ? ? 10 840 ms s (3) (3, 7) 131 132 internal oscillator frequency test frequency - divided from internal oscillator * f osc f osctst 7.6 0.95 8 1 8.4 1.05 mhz mhz (7) (1) 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 serial interface timing (see figure 6 , c miso 80 pf, r miso 10 k ) clock (sclk) period (10% of v cc to 10% of v cc ) clock (sclk) high time (90% of v cc to 90% of v cc ) clock (sclk) low time (10% of v cc to 10% of v cc ) clock (sclk) rise time (10% of v cc to 90% of v cc ) clock (sclk) fall time (90% of v cc to 10% of v cc ) cs asserted to sclk high (cs = 10% of v cc to sclk = 10% of v cc ) cs asserted to miso valid (cs = 10% of v cc to miso = 10/90% of v cc ) data setup time (mosi = 10/90% of v cc to sclk = 10% of v cc ) mosi data hold time (sclk = 90% of v cc to mosi = 10/90% of v cc ) miso data hold time (sclk = 90% of v cc to miso = 10/90% of v cc ) sclk low to data valid (sclk = 10% of v cc to miso = 10/90% of v cc ) sclk low to cs high (sclk = 10% of v cc to cs = 90% of v cc ) cs high to miso disable (cs = 90% of v cc to miso = hi z) cs high to cs low (cs = 90% of v cc to cs = 90% of v cc ) sclk low to cs low (sclk = 10% of v cc to cs = 90% of v cc ) cs high to sclk high (cs = 90% of v cc to sclk = 90% of v cc ) * * * * * * * * * * * * * t sclk t sclkh t sclkl t sclkr t sclkf t lead t access t setup t hold_in t hold_out t valid t lag t disable t csn t clkcs t csclk 120 40 40 ? ? 60 ? 20 10 0 ? 60 ? 526 60 60 ? ? ? 15 15 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 40 28 ? 60 ? ? ? 40 ? 60 ? ? ? ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (3) (3) (3) (19) (19) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (19)
sensors 10 freescale semiconductor mma685x figure 5. power-up timing figure 6. serial interface timing v cc por v rega v reg devres v cc_uv_f v rega_uv_f devres flag cleared by user v cc_uv_r v rega_uv_r v reg_uvr_r v reg_uvr_f time note: v rega & v reg rise and fall slopes will be dependent on output capacitance and load current t sclk sclk mosi cs miso t sclkh t sclkl t access t sclkr t sclkf t lead t csn t setup t hold_in t valid t disable t hold_out t lag t clkcs t csclk
sensors freescale semiconductor 11 mma685x 3 functional description 3.1 customer accessible data array a customer accessible data array allows for each device to be customized. the array consists of an otp factory programma- ble block and read/write registers for de vice programmability and stat us. the otp and writable regi ster blocks incorporate inde - pendent crc circuitry for fault detection (reference section 3.2 ). the writable register block includes a locking mechanism to prevent unintended changes during normal operati on. portions of the array are reserved for factory-programmed trim values. the customer accessible data is shown in ta b l e 3 . type codes f: factory programmed otp location r/w: read/write register r: read-only register n/a: not applicable table 3. customer accessible data location bit function type addr register 7 6 5 4 3 2 1 0 $00 sn0 sn[7] sn[6] sn[5] sn[4] sn[3] sn[2] sn[1] sn[0] f $01 sn1 sn[15] sn[14] sn[13] sn[12] sn[11] sn[10] sn[9] sn[8] $02 sn2 sn[23] sn[22] sn[21] sn[20 ]sn[19]sn[18]sn[17]sn[16] $03 sn3 sn[31] sn[30] sn[29] sn[28] sn[27] sn[26] sn[25] sn[24] $04 reserved reserved reserved reserved rese rved reserved reserved reserved reserved $05 reserved reserved reserved reserved reserved reserved reserved reserved reserved $06 fctcfg stmag 0 0 0 0 0 0 0 $07 invalid address: ?invalid register request? $08 pn pn[7] pn[6] pn[5] pn[4] pn[3] pn[2] pn[1] pn[0] $09 invalid address: ?invalid register request? $0a devctl res_1 res_0 reserved reserved reserved reserved reserved reserved r/w $0b devcfg reserved reserved endinit sd ofmon a_cfg[2] a_cfg[1] a_cfg[0] $0c devcfg_x st reserved reserved reserved lpf[3] lpf[2] lpf[1] lpf[0] $0d invalid address: ?invalid register request? $0e armcfg reserved reserved aps[1] aps[0] aws_n[1] aws_n[0] aws_p[1] aws_p[0] $0f invalid address: ?invalid register request? $10 armt_p at_p[7] at_p[6] at_p[5] at_p[4] at_p[3] at_p[2] at_p[1] at_p[0] $11 invalid address: ?invalid register request? $12 armt_n at_n[7] at_n[6] at_n[5] at_n[4] at_n[3] at_n[2] at_n[1] at_n[0] $13 invalid address: ?invalid register request? $14 devstat unused ide sdov devinit misoerr 0 offset devres r $15 count count[7] count[6] count[5] count[4] count[3] count[2] count[1] count[0] $16 offcorr_x offcorr_x[7] offcorr_x[6] offcorr_x[5] offcorr_ x[4] offcorr_x[3] offcorr_x[2] offcorr_x[1] offcorr_x[0] $17 invalid address: ?invalid register request? $1c reserved reserved reserved reserved reserved reserved reserved reserved reserved $1d reserved reserved reserved reserved reserved reserved reserved reserved reserved
sensors 12 freescale semiconductor mma685x 3.1.1 device serial number registers a unique serial number is programmed into the serial number registers of each mma685x device during manufacturing. the serial number is composed of the following information: serial numbers begin at 1 for all produced devices in each lo t, and are sequentially assigned. lot numbers begin at 1 and are sequentially assigned. no lot will contain more devices than ca n be uniquely identified by the 13-bit serial number. depending on lot size and quantities, all possible lot numbers and serial numbers may not be assigned. the serial number registers are included in the otp shadow register array crc verification. reference section 3.2.1 for de- tails regarding the crc verification. beyond this, the contents of the serial number registers have no impact on device operati on or performance, and are only used for traceability purposes. 3.1.2 reserved registers these reserved registers are read-only and have no impact on device operation or performance. 3.1.3 factory configuration registers the factory configuration register is a o ne time programmable, read only register whic h contains customer specific device con- figuration information that is programmed by freescale. 3.1.3.1 self-test magnitude selection bits (stmag) the self-test magnitude selection bits indica te if the nominal self-test deflection va lue is set to the low or high value as sh own in the table below. bit range content s12 - s0 serial number s31 - s13 lot number table 4. reserved registers location bit addressregister76543210 $04 reserved reserved reserved reserved reserved reserved reserved reserved reserved $05 reserved reserved reserved reserved reserved reserved reserved reserved reserved table 5. factory configuration register location bit addressregister76543210 $06fctcfgstmag0000000 stmag full-scale acceleration range nominal self-test deflection value (reference section 2.4 ) 0 60g st low 1 > 60g st hi
sensors freescale semiconductor 13 mma685x 3.1.4 part number register (pn) the part number register is a one time progr ammable, read only register which contai ns two digits of the device part number to identify the axis and range information. the contents of this register have no impact on device operation or performance. 3.1.5 device control register (devctl) the device control register is a read-writ e register which contains device control operations that can be applied during both initialization and normal operation. 3.1.5.1 reset control (res_1, res_0) a series of three consecutive register wr ite operations to the reset control bits in the devctl register will cause a device re set. to reset the internal digital circuitry, the following register write operations must be perfor med in the order shown below. th e reg- ister write operations must be consecutive spi command s in the order shown or the device will not be reset. the response to the register write returns ?0? for res_1 and res_0. a register read of res_1 and res_0 returns ?0? and terminates the reset sequence. 3.1.5.2 reserved bits (devctl[5:0]) bits 5 through 0 of the devctl register are reserved. a write to the reserved bits must always be logic ?0? for normal device operation and performance. table 6. part number register location bit addressregister76543210 $08 pn pn[7] pn[6] pn[5] pn[4] pn[3] pn[2] pn[1] pn[0] pn register value range reference section 2.4 decimal hex 51 $33 20 52 $34 35 53 $35 50 54 $36 75 55 $37 100 56 $38 60 51 $33 20 table 7. device control register location bit addressregister76543210 $0a devctl res_1 res_0 reserved reserved reserved reserved reserved reserved reset value 00000000 register write to devctl res_1 res_0 effect spi register write 1 0 0 no effect spi register write 2 1 1 no effect spi register write 3 0 1 device reset
sensors 14 freescale semiconductor mma685x 3.1.6 device configuration register (devcfg) the device configuration register is a read/ write register which contains data for g eneral device configuration. the register c an be written during initialization but is locked once the endinit bi t is set. this register is included in the writable register crc check. refer to section 3.2.2 for details. 3.1.6.1 reserved bits (reserved) bits 6 and 7 of the devcfg register are re served. a write to the reserved bits must always be logic ?0? for normal device op- eration and performance. 3.1.6.2 end of initialization bit (endinit) the endinit bit is a control bit used to indicate that the user has completed all device and system leve l initialization tests, and that mma685x will operate in normal mode. once the endinit bit is set, writes to all writable register bits are inhibited e xcept for the devctl register. once written, the endinit bit can only be cleared by a device reset. the writable register crc check (reference section 3.2.2 ) is only enabled when the endinit bit is set. 3.1.6.3 sd bit the sd bit determines the format of a cceleration data results. if the sd bit is set to a logic ?1?, unsigned results are transmitted, with the zero-g level represented by a nominal value of 512. if the sd bit is cleared, signed result s are transmitted, with the zero- g level represented by a nominal value of 0. 3.1.6.4 ofmon bit the ofmon bit determines if the offset monitor circuit is enabled . if the ofmon bit is set to a lo gic ?1?, the offset monitor i s enabled. refer to section 3.8.5 for more information. if the ofmon bit is cleared, the offset monitor is disabled. table 8. device configuration register location bit addressregister76543210 $0b devcfg reserved reserved endinit sd ofmon a_cfg[2] a_cfg[1] a_cfg[0] reset value 00000000 sd operating mode 1 unsigned data output 0 signed data output ofmon operating mode 1 offset monitor circuit enabled 0 offset monitor circuit disabled
sensors freescale semiconductor 15 mma685x 3.1.6.5 arm configurat ion bits (a_cfg[2:0]) the arm configuration bits (a_cfg[2:0]) select the mode of operation for the arm/pcm pins. 3.1.7 axis configuration register (devcfg_x) the axis configuration register is a read/write regi ster which contains axis specific c onfiguration information. this register can be written during initialization, but is lo cked once the endinit bit is set. this re gister is included in the writable register crc check. refer to section 3.2.2 for details 3.1.7.1 self-test control (st) t he st bit enables and disables the self-test circuitry. self-test circuitry is enabled if a logic ?1? is written to st and the endinit bit has not been set. enabling the self-test circuitry results in a positive acceleration value. self-test deflection values ar e specified in section 2.4 . st is always cleared following internal reset. when the self-test circuitry is active, th e offset cancellation block and the offset monitor status are suspended, and the stat us bits in the acceleration data request response will indicate ?self-test active?. reference section 3.8.4 and section 4.2 for de- tails. when the self-test circuitry is disabled by clearing the st bit, the offset monitor remains disabled until the time t st_omb spec- ified in section 2.4 expires. however, the status bits in the accelerati on data request response will immediately indicate that self-test has been deactivated. 3.1.7.2 reserved bits (reserved) bits 6 through 4 of the devcfg_x register are reserved. a write to the reserved bits must always be logic ?0? for normal device operation and performance. table 9. arming output configuration a_cfg[2] a_cfg[1] a-cfg[0] operating mode output type reference 0 0 0 arm output disabled hi impedance 0 0 1 pcm output digital output section 3.8.10 0 1 0 moving average mode active high with pull-down current section 3.8.9.1 0 1 1 moving average mode active low with pull-up current section 3.8.9.1 1 0 0 count mode active high with pull-down current section 3.8.9.2 1 0 1 count mode active low with pull-up current section 3.8.9.2 1 1 0 unfiltered mode active high with pull-down current section 3.8.9.3 1 1 1 unfiltered mode active low with pull-up current section 3.8.9.3 table 10. axis configuration registers location bit addressregister76543210 $0c devcfg_x st reserved reserved reserved lpf[3] lpf[2] lpf[1] lpf[0] reset value 00000000
sensors 16 freescale semiconductor mma685x 3.1.7.3 low-pass filter se lection bits (lpf[3:0]) the low pass filter selection bit sele cts a low-pass filter as shown in ta b l e 11 . refer to section 3.8.3 for details regarding filter configurations. note: filter characteristics do no t include g-cell frequency response. 3.1.8 arming configuration registers (armcfg) the arming configuration register contains configuration information for the arming func tion. the values in this register are o nly relevant if the arming function is operating in moving average mode, or count mode. this register can be written during initialization but is locked once the endinit bit is set. refer to section 3.1.6.2 . this register is included in the writable register crc check. refer to section 3.2.2 for details. 3.1.8.1 reserved bits (reserved) bits 7 through 6 of the armcfg register are reserved. a write to the reserved bits must always be logic ?0? for normal device operation and performance. table 11. low pass filter selection bits lpf[3] lpf[2] lpf[1] lpf[0] low pass filter selected nominal sample rate ( s) 0 0 0 0 100 hz, 4 pole 8 0 0 0 1 300 hz, 4 pole 8 0 0 1 0 400 hz, 4 pole 8 0 0 1 1 800 hz, 4 pole 8 0 1 0 0 1000 hz, 4 pole 8 0 1 0 1 400 hz, 3 pole 8 0 1 1 0 reserved reserved 0 1 1 1 reserved reserved 1 0 0 0 50 hz, 4 pole 16 1 0 0 1 150 hz, 4 pole 16 1 0 1 0 200 hz, 4 pole 16 1 0 1 1 400 hz, 4 pole 16 1 1 0 0 500 hz, 4 pole 16 1 1 0 1 200 hz, 3 pole 16 1 1 1 0 reserved reserved 1 1 1 1 reserved reserved table 12. arming configuration register location bit addressregister76543210 $0e armcfg reserved reserved aps[1] aps[0] aws_n[1] aws_n[0] aws_p[1] aws_p[0] reset value 00001111
sensors freescale semiconductor 17 mma685x 3.1.8.2 arming pulse stretch (aps[1:0]) the aps[1:0] bit sets t he programmable pulse stretch time for the arming ou tputs. refer to section 3.8.9 for more details re- garding the arming function. 3.1.8.3 arming window size (aws_x[1:0]) the aws_x[1:0] bit has a different f unction depending on the state of the a_cfg bits in the devcfg register. if the arming function is set to moving average mode, the aws bi ts set the number of acceleration samples used for the arming function moving average. the number of samples is set independen tly for polarity. if the arming function is set to count mode, the aws bits set the sample count limit for the arming function. the sample count limit is set independently. refer to section 3.8.9 for more details regarding the arming function. table 13. arming pulse stretch definitions aps[1] aps[0] pulse stretch time (1) (typical oscillator) 1.pulse stretch times are derived from the internal os cillator, so the tolerance on this oscillator applies. 00 0 ms 0 1 16.256 ms - 16.384 ms 1 0 65.408 ms - 65.536 ms 1 1 261.888 ms - 262.016 ms table 14. positive arming window size definitions (movi ng average mode) aws_p[1] aws_p[0] positive window size 00 2 01 4 10 8 11 16 table 15. negative arming window size definitions (moving average mode) aws_n[1] aws_n[0] negative window size 00 2 01 4 10 8 11 16 table 16. arming count limit definitions (count mode) aws_n[1] aws_n[0] aws_p[1] aw s_p[0] sample count limit don?t care don?t care 0 0 1 don?t care don?t care 0 1 3 don?t care don?t care 1 0 7 don?t care don?t care 1 1 15
sensors 18 freescale semiconductor mma685x 3.1.9 arming threshold registers (armt_p, armt_n) these registers contain the positive and negative threshol ds to be used by the arming function. refer to section 3.8.9 for more details regarding the arming function. these registers can be written during initialization but are locked once the endinit bit is set. refer to section 3.1.6.2 . these registers are included in the writ able register crc check. refer to section 3.2.2 for details. the values programmed into the threshold registers are the th reshold values used for the arming function as described in section 3.8.9 . the threshold registers hold independent unsigned 8-bit values for polarity. each threshold increment is equivalent to one output lsb. table 18 shows examples of some threshold regist er values and the corresponding threshold. if either the positive or negative threshold is programmed to $00, comparisons are disabled for only that polarity. the arming function still operates for the opposite polarity. if both the positive and negative arming thresholds are programmed to $00, t he arming function is disabled, and the output pin is disabled, regardless of the value of the a_cfg bits in the devcfg register. 3.1.10 device status register (devstat) the device status register is a read-only register. a read of th is register clears the status fl ags affected by transient condi tions. reference section 4.5 for details on the mma685x response for each status condition. 3.1.10.1 unused bit (unused) the unused bit has no impact on operation or performance. when read this bit may be ?1? or ?0?. 3.1.10.2 internal data error flag (ide) the internal data error flag is set if a customer or otp regi ster data crc fault or other internal fault is detected as defined in section 4.5.5 . the internal data error flag is cleared by a read of th e devstat register. if the error is associated with a crc fault in the writable register array, the fault will be re-asserted a nd will require a device reset to clear. if the error is associa ted with the data stored in the fuse array, the fault will be re-asserted even after a device reset. 3.1.10.3 sigma delta modulator over range flag (sdov) the sigma delta modulator over range flag is set if the sigma delta modulator becomes saturated. the sdov flag is cleared by a read of the devstat register. table 17. arming threshold registers location bit addressregister76543210 $10 armt_p at_p[7] at_p[6] at_p[5] at_p[4] at_p[3] at_p[2] at_p[1] at_p[0] $12 armt_n at_n[7] at_n[6] at_n[5] at_n[4] at_n[3] at_n[2] at_n[1] at_n[0] reset value 00000000 table 18. threshold register value examples axis type programmed thresholds range (g) sensitivity (g/lsb) positive (decimal) negative (decimal) positive threshold (g) negative threshold (g) 20 0.04097 100 50 4.10 -2.05 20 0.04097 255 0 10.45 disabled 50 0.1024 50 20 5.12 -2.05 120 0.24414 20 10 4.88 -2.44 table 19. device status register location bit addressregister76543210 $14 devstat unused ide sdov devinit misoerr 0 offset devres
sensors freescale semiconductor 19 mma685x 3.1.10.4 device initializ ation flag (devinit) the device initialization flag is set during the interval between negation of internal reset and completion of internal device ini- tialization. devinit is cl eared automatically. the device init ialization flag is not affected by a read of the devstat register . 3.1.10.5 spi miso data mism atch error flag (misoerr) the miso data mismatch flag is set when a miso data mismatch fault occurs as specified in section 4.5.2 . the misoerr flag is cleared by a read of the devstat register. 3.1.10.6 offset monitor over range flags (offset) the offset monitor over range flag is set if the acceleration signal reaches the specified offs et limit. the offset monitor ove r range flags are cleared by a read of the devstat register. 3.1.10.7 device reset flag (devres) the device reset flag is set during device initialization following a device reset. the device reset flag is cleared by a read of the devstat register. 3.1.11 count register (count) the count register is a read-only register which provides the current value of a fr ee-running 8-bit counter derived from the pr i- mary oscillator. a 10-bit pre-scaler divides the primary oscillat or frequency by 1024. thus, the value in the register increase s by one count every 128 s and the counter rolls over every 32.768 ms. 3.1.12 offset correction value registers (offcorr) the offset correction value register is a read-only register wh ich contain the most recent offs et correction increment / decre- ment value from the offset cancellation circuit. the value stored in this register indicates t he amount of offset correction be ing applied to the spi output data. the values have a resolution of 1 lsb. 3.1.13 reserved registers (reserved) registers $1c and $1d are reserved. a write to the reserved bi ts must always be logic ?0? for normal device operation and performance. table 20. count register location bit addressregister76543210 $15 count count[7] count[6] co unt[5] count[4] count[3] co unt[2] count[1] count[0] reset value 00000000 table 21. offset correction value register location bit addressregister76543210 $16 offcorr_x offcorr_x[7] offcorr_x[6] o ffcorr_x[5] offcorr_x[4] offcorr_x[3] o ffcorr_x[2] offcorr_x[1] offcorr_x[0] reset value 00000000 table 22. reserved registers location bit addressregister76543210 $1c reserved reserved reserved reserved res erved reserved reserved reserved reserved $1d reserved reserved reserved reserved res erved reserved reserved reserved reserved reset value 00000000
sensors 20 freescale semiconductor mma685x 3.2 customer accessible data array crc verification 3.2.1 otp shadow register array crc verification the otp shadow register array is verified for errors using a 3-bit crc. the crc veri fication uses a generator polynomial of g(x) = x 3 + x + 1, with a seed value = ?111?. if a crc error is detected in the otp array, the ide bit is set in the devstat register. 3.2.2 writable register crc verification the writable registers in the data array are verified for erro rs using a 3-bit crc. the crc verification is enabled only when the endinit bit is set in the devcfg register. the cr c verification uses a generat or polynomial of g(x) = x 3 + x + 1, with a seed value = ?111?. if a crc error is detected in the writable re gister array, the ide bit is set in the devstat register. 3.3 voltage regulators separate internal voltage regulators supply the analog and digita l circuitry. external filter ca pacitors are required, as shown in figure 1 . the voltage regulator module includes voltage monitoring circ uitry which indicates a device reset until the external sup- ply and all internal regulated voltages are within predetermin ed limits. a reference generator provides a stable voltage which is used by the ? converters. figure 7. power supply c rega c reg v cc tracking regulator voltage regulator reference generator v rega = 2.50 v digital logic dsp otp array primary oscillator ? converter bias generator trim trim v ref = 1.250 v v reg = 2.50 v bandgap reference tracks v rega
sensors freescale semiconductor 21 mma685x figure 8. voltage monitoring 3.3.1 c reg failure detection the digital supply voltage regulator is designed to be uns table with low capacitance. if the connection to the v reg capacitor becomes open, the digital supply voltage will oscillate and cause ei ther an under voltage, or over voltage failure within one i nter- nal sample time. this failure will result in one of the following: 1. the devres flag in the devstat register will be set. mma685x will respond to spi acceleration requests as defined in ta b l e 2 7 . 2. mma685x will be held in reset and be non-responsive to spi requests. 3.3.2 c rega failure detection the analog supply voltage regulator is designed to be unst able with low capacitance. if the connection to the v rega capacitor becomes open, the analog supply voltage will oscillate and caus e either an under voltage, or ov er voltage failure within one in - ternal sample time. the devres flag in the devstat register will be set. mma685xmma685x will respond to spi acceleration requests as defined in ta b l e 2 7 . 3.3.3 v ss and v ssa ground loss monitor mma685x detects the loss of ground connection to either v ss or v ssa . a loss of ground connection to v ss will result in a v reg over voltage failure. a loss of ground connection to v ssa will result in a v reg undervoltage failure. both failures result in a device reset. 3.3.4 spi initiated reset in addition to voltage monitoring, a device reset can be initiat ed by a specific series of thre e write operations involving the res_1 and res_0 bits in the devctl register. reference section 3.1.5.1 . for details regarding the spi initiated reset. 3.4 internal oscillator mma685x includes a factory trimmed oscillator as specified in section 2.6 . 3.4.1 oscillator monitor the count register in the customer accessible array is a read-on ly register which provides the current value of a free-running 8-bit counter derived from the primary oscillator. a 10-bit pre- scaler divides the primary oscillator by 1024. thus, the value in the count register increases by one count every 128 s, and the register rolls over every 32.768 ms. the spi master can periodi- cally read the count register, and verify the difference betw een subsequent register reads against the system time base. 1. the spi access rates and deviations must be take n into account for this oscillator verification. set devres flag v cc v rega v reg v ref monitor bandgap v ccuv v regov v reguv v regauv v regaov v refov v refuv ground loss monitor v reg por v bgmon v porref note: no external access to reference voltage limits verified by characterization only
sensors 22 freescale semiconductor mma685x 3.5 transducer the mma685x transducer is an overdamped mass-spring-damper system described by the following transfer function: where: = damping ratio n = natural frequency = 2 ?? f n reference section 2.4 for transducer parameters. 3.6 self-test interface the self-test interface applies a voltage to the g-cell, causing deflection of the proof mass. the self-test interface is contr olled through spi write operations to th e devcfg_x register described in section 3.1.7 . the endinit bit in the devcfg register must also be low to enable self-test. a diag ram of the self-test interface is shown in figure 9 . figure 9. self-test interface the raw self-test deflection can be verified against raw self-test limits using the following equation: where: st min the minimum self-test deflection ov er temperature as specified in section 2.4 . st max the maximum self-test deflection over temperature as specified in section 2.4 . sens the sensitivity of the device sens the sensitivity tolerance hs () n 2 s 2 2 n s ?? ? n 2 ++ --------------------------------------------------------- = self-test voltage generator endinit st g-cell endinit st minlimit floor st min () sens 1 sens + () ----------------------------------------------------------- ? = st maxlimit ceil st max () sens 1 sens ? () ---------------------------------------------------------- - ? =
sensors freescale semiconductor 23 mma685x 3.7 ? converters two sigma delta converters provide the interface bet ween the g-cell and the dsp. the output of each ? converter is a data stream at a nominal frequency of 1 mhz. figure 10. ? converter block diagram 3.8 digital signal processing block a digital signal processing (dsp) block is used to perform si gnal filtering and compensation op erations. a diagram illustrating the signal processing flow is shown in figure 11 . figure 11. signal chain diagram 1-bit quantizer z -1 1 - z -1 z -1 1 - z -1 first integrator second integrator 1 = 1 2 2 v x c int1 g-cell c bot c top c = c top - c bot ? _out v = 2 v ref adc dac v = c x v x / c int1 ? _out to spi to arm a b c eg to spi h i df sinc filter section 3.8.2 low pass filter section 3.8.3 compensation section 3.8.6 interpolation section 3.8.7 offset cancellation section 3.8.4 offset cancellation output scaling raw output scaling arm/pcm output section 3.8.9 section 3.8.10 table 23. mma685x signal chain characteristics description sample time ( s) data width bits over bits effective bits rounding resolution bits typical block latency reference a ? 1 1 1 ? 3.2 s section 3.7 b sinc filter 8 14 13 ? 11.2 s section 3.8.2 c low pass filter 8/16 20 6 10 4 reference section 3.8.3 section 3.8.3 d compensation 8/16 20 6 10 4 7.875 s section 3.8.6 e interpolation 4/8 20 6 10 4 t s / 2 section 3.8.7 f offset cancellation 256 20 6 10 4 n/a section 3.8.4 g, h spi output 4/8 ? ? 10 ? t s / 2 ? i pcm output 4/8 ? ? 9 ? ? section 3.8.10
sensors 24 freescale semiconductor mma685x 3.8.1 dsp clock the dsp is clocked at 8 mhz, with an effe ctive 6mhz operating frequency. the clock to the dsp is disabled for 1 clock prior to each edge of the ? modulator clock to minimize noise during data conversion. the bit streams from the two ? converters are processed through independent data paths within the dsp. figure 12. clock generation 3.8.2 decimation sinc filter the serial data stream produced by the ? converter is decimated and converted to parallel values by a 3rd order 16:1 sinc filter with a decimation factor of 8 or 16, depending on the low pass filter selected. figure 13. sinc filter response, t s = 8 s 8 mhz osc 6 mhz digital 1mhz modulator hz () 1z 16 ? ? 16 1 z 1 ? ? () ------------------------------------ - 3 =
sensors freescale semiconductor 25 mma685x 3.8.3 low pass filter data from the sinc filter is processed by an infinite impulse response (iir) low pass filter. mma685x provides the option for one of twelve low-pass filters. the filter is selected with the lpf[3:0] bits in the devcfg_x register. the filter selection options are listed in section 3.1.7.3 , table 11 . response parameters for the low-pass filter are spec- ified in section 2.4 . filter characteristics are illustrated in figures 14 , 15 , 16 , 17 , 18 and 19 . note: low pass filter figures do not include g-cell frequency response. table 24. low pass filter coefficients description sample time ( s) filter coefficients group delay 50 hz lpf 16 n 0 2.08729034056887e-10 d 0 1 26816/f osc n 1 8.349134489240434e-10 d 1 -3.976249694824219 n 2 1.25237777794924e-09 d 2 5.929003009577855 100 hz lpf 8 n 3 8.349103355433541e-10 d 3 -3.929255528257727 n 4 2.087307211059861e-10 d 4 0.9765022168437554 150 hz lpf 16 n 0 1.639127731323242e-08 d 0 1 9024/f osc n 1 6.556510925292969e-08 d 1 -3.928921222686768 n 2 9.834768482194806e-08 d 2 5.789028996785419 300 hz lpf 8 n 3 6.556510372902331e-08 d 3 -3.791257019240902 n 4 1.639128257923422e-08 d 4 0.9311495074496179 200 hz lpf 16 n 0 5.124509334564209e-08 d 0 1 6784/f osc n 1 2.049803733825684e-07 d 1 -3.905343055725098 n 2 3.074705789151505e-07 d 2 5.72004239520561 400 hz lpf 8 n 3 2.049803958150164e-07 d 3 -3.723967810019985 n 4 5.124510693742625e-08 d 4 0.9092692903507213 200 hz lpf 3-pole 16 n 0 2.720393240451813e-06 d 0 1 5632/f osc n 1 8.161179721355438e-06 d 1 -2.931681632995605 n 2 8.161180123840722e-06 d 2 2.865296718275204 400 hz lpf 3-pole 8 n 3 2.720393634345496e-06 d 3 -0.9335933215174919 n 4 0d 4 0 400 hz lpf 16 n 0 7.822513580322266e-07 d 0 1 3392/f osc n 1 3.129005432128906e-06 d 1 -3.811614513397217 n 2 4.693508163398543e-06 d 2 5.450666051045118 800 hz lpf 8 n 3 3.129005428784364e-06 d 3 -3.465805771100349 n 4 7.822513604678875e-07 d 4 0.8267667478030489 500 hz lpf 16 n 0 1.865386962890625e-06 d 0 1 2688/f osc n 1 7.4615478515625e-06 d 1 -3.765105724334717 n 2 1.119232176112846e-05 d 2 5.319861050818872 1000 hz lpf 8 n 3 7.4615478515625e-06 d 3 -3.34309015036024 n 4 1.865386966264658e-06 d 4 0.7883646729233078 hz () n 0 n 1 z 1 ? ? () n 2 z 2 ? ? () n 3 z 3 ? ? () n 4 z 4 ? ? () ++++ d 0 d 1 z 1 ? ? () d 2 z 2 ? ? () d 3 z 3 ? ? () d 4 z 4 ? ? () ++++ ------------------------------------------------------------------------------------------------------------------------------- --------- - =
sensors 26 freescale semiconductor mma685x figure 14. low-pass filter characteristics: f c = 100 hz, poles = 4, t s = 8 s
sensors freescale semiconductor 27 mma685x figure 15. low-pass filter characteristics: f c = 300 hz, poles = 4, t s = 8 s
sensors 28 freescale semiconductor mma685x figure 16. low-pass filter characteristics: f c = 400 hz, poles = 4, t s = 8 s
sensors freescale semiconductor 29 mma685x figure 17. low-pass filter characteristics: f c = 400 hz, poles = 3, t s = 8 s
sensors 30 freescale semiconductor mma685x figure 18. low-pass filter characteristics: f c = 800 hz, poles = 4, t s = 8 s
sensors freescale semiconductor 31 mma685x figure 19. low-pass filter characteristics: f c = 1000 hz, poles = 4, t s = 8 s
sensors 32 freescale semiconductor mma685x 3.8.4 offset cancellation mma685x provides the option to read offset cancelled acceleration data via the spi by clearing the oc bit in the spi command (reference section 4.1 ). a block diagram of the offset cancellation is shown in figure 20 , and response parameters are specified in section 2.4 and in ta b l e 2 5 . figure 20. offset cancellation block diagram in normal operation, the offset cancellation circuit computes a 24,576 sample running average of the acceleration data down- sampled to 256 s. the running average is compared against positive an d negative thresholds to determine the offset correction value that will be applied to the acceleration data. during start up, three phases of moving average sizes are used to allow for faster convergence of misuse input signals. refer to table 25 for offset cancellation timing information during startup and normal operation. when the self-test circuitry is active, t he offset cancellation block and the offset monitor block are suspended, and the offse t correction value is constant. once the self-test circuitry is di sabled, the offset cancellation block remains suspended for the time t st_omb to allow the acceleration output to return to it?s nominal offset. 3.8.5 offset monitor mma685x provides the option for an offset monitor circuit. the offset monitor circuit is enabled when the ofmon bit in the devcfg register is programmed to a logic ?1?. the output of the offset cancellation circuit is compared against a high and low threshold. if the offset correction value exceeds either the offthr pos , or offthr neg threshold, an offset over range con- dition is indicated. the offset correction value update rate is listed in table 25 : ?maximum slew rate?. because the offset monitor uses this value, the offset monitor will also update at this rate. the time to indicate an offset over range is dependent upon the input signal. the offset monitor status remains frozen dur ing self-test, because the offset monitor is based on the offset cancellation circu it, which is also suspended during self-test. the offset monitor is disabled for 2.1 seconds following reset regardless of the stat e of the ofmon bit. 3.8.6 signal compensation mma685x includes internal otp and signal processing to compensa te for sensitivity error and offset error. this compensation is necessary to achieve the specified parameters in section 2.4 . table 25. offset cancellation timing specifications phase start time of phase (from por) typical time in phase (ms) # of samples in phase samples averaged off_corr_value update rate (ms) averaging period (ms) maximum slew rate (lsb/s) averaging filter -3db frequency (hz) start 1 t op 524.288 2048 48 2.048 12.288 122.1 36.05 start 2 t op + 524.288 524.288 2048 384 16.38 98.304 15.26 4.506 start 3 t op + 1048.576 524.288 2048 3072 131.1 786.432 1.907 0.5632 normal t op + 1572.864 ? ? 24576 1049 6291.456 0.2384 0.07040 accumulator t1 up to 4096 samples shift lpf out t2 t5 t4 t3 t6 offset inc/dec off corrp off corrn off thn off thp inc dec downsampled to 256 s off_corr_value offthr neg offthr pos off_err off_err correction for start phase oc out
sensors freescale semiconductor 33 mma685x 3.8.7 data interpolation mma685x includes 2 to 1 data interpolation to minimize the system sample jitter. each result produced by the digital signal processing chain is delayed one half of a sample time, and th e interpolated value of successive samples is provided between sample times. this operation is illustrated in figure 21 . figure 21. data interpolation timing the effect of this interpolation at the system level is a 50% reduction in sample jitter. figure 22 shows the resulting output data for an input signal. figure 22. data interpolation example s n-3 s n-2 t t s n-1 t s t s s n-1 t s s n s n-2 s n3 ? s n2 ? + 2 ------------------------------- - s n2 ? s n1 ? + 2 ------------------------------- - s n1 ? s n + 2 ------------------------ - s n-3 response to spi acceleration request occurring in this window receives interpolated sample response to spi acceleration request occurri ng in this window receives true sample. internal sample rate output sample rate 40 45 50 55 60 65 70 75 80 0 5 10 15 20 25 30 35 40 time counts input signal internally sampled signal interpolated samples internally sampled values earliest transmission point of interpolated values earliest transmission point of internally sampled values window of transmission for sampled values (maximum: t s / 2) window of transmission for interpolated values (maximum: t s / 2) fixed latency: t s / 2 = signal jitter =
sensors 34 freescale semiconductor mma685x 3.8.8 acceleration data timing the mma685x spi uses a request/response protocol, where a spi transfer is completed through a sequence of 2 phases. reference section 4 for more details regarding the spi protocol. in order to provide the most recent acceleration data for each request, mma685x latches the associated data for an acceleration request at the falling edge of cs for the acceleration response message (the subsequent spi transfer). the most recent sample available from the dsp (i ncluding interpolation), is latched, pro - viding a maximum latency of 1* t s relative to the falling edge of cs . figure 23. acceleration data timing 3.8.9 arming function mma685x provides the option for an arming function with 3 modes of operat ion. the operation of the arming function is se- lected by the state of the a_cfg bits in the devcfg register. reference section 4.5 for the operation of the arming function with except ion conditions. error conditions do not impact prior arming function responses. if an error occurs after an arming activation, the corresponding pulse stretch for the existing armi ng condition will continue. however, new acceleration reads will not update the arming function regardless of the acceleration val ue. 3.8.9.1 arming function: moving average mode in moving average mode, the arming functi on runs a moving average on the offset cancelled output. the number of samples used for the moving average (k) is programmable via the aws_x[1:0] bits in the ar mcfgx register. reference section 3.1.8 for register details. arm_ma n = (oc n + oc n-1 + ... + oc n+1-k )/k where n is the current sample. the sample rate is determined by the spi acceleration data sample rate. at the falling edge of cs for an acceleration data spi response, the moving average is updated with a new sample. reference figure 26 . the spi acceleration data sample rate must meet the minimum time between requests (t acc_req_x ) specified in section 2.5 . the moving average output is compared against positive and ne gative 8-bit thresholds that are programmed via the armt_x registers. reference section 3.1.9 for register details. if the moving average equal s or exceeds either threshold, an arming con- dition is indicated, the arm output is asserted, and the pulse stretch counter is set as described in section 3.8.9.4 . sclk mosi miso cs request accel. request accel. acceleration data acceleration data request accel. request accel. acceleration data acceleration data latched arm function updated if applicable
sensors freescale semiconductor 35 mma685x the arm output is de-asserted only w hen the pulse stretch counter expires. figure 26 shows the arming output operation for different spi conditions. figure 24. arming function block diagram - moving average mode 3.8.9.2 arming function: count mode in count mode, the arming function comp ares each input sample against positive and negative thresholds that are pro- grammed via the armt_x registers. reference section 3.1.9 for register details. if the sample equals or exceeds either thresh- old, a sample counter is incremented. if the sample does not exceed either threshol d, the sample counter is reset to zero. the sample rate is determined by the spi acceleration data sample rate. at the falling edge of cs for an acceleration data spi response, a new sample is compared against the thresholds. reference figure 26 . the spi acceleration data sample rate must meet the minimum time between requests (t acc_req_x ) specified in section 2.5 . a sample count limit is programmable via the aws_x[1:0] bits in the armcfg register. if t he sample count reaches the pro- grammable sample count limit, an arming condition is indicated, the arm output is asserted and the pulse stretch counter is set as described in section 3.8.9.4 . the arm output is de-asserted only w hen the pulse stretch counter expires. figure 26 shows the arming output operation for different spi conditions. figure 25. arming function block diagram - count mode offset cancellation aws_p[1:0] aps[3:0] pulse stretch arm gating i/o armt_n[7:0] armt_p[7:0] moving average positive moving average negative aws_n[1:0] offcanc_arm[10:0] armt_n[7:0] offset cancellation aws_p[1:0] aps[1:0] pulse stretch arm armt_p[7:0] gating i/o 1-4 sample counter offcanc_arm[10:0]
sensors 36 freescale semiconductor mma685x figure 26. mma685x arming condition, moving average and count mode 3.8.9.3 arming function: unfiltered mode on the falling edge of cs for an acceleration response, the most recent available dsp sample is compared against positive and negative thresholds that are programm ed via the armt_x registers. reference section 3.1.9 for register details. if the sam- ple equals or exceeds either threshold, an arming condition is indicated. once an arming condition is indicated fo r the arm output is asserted when cs is asserted and the miso data includes an acceleration response. the pulse stretch function is not applied in unfiltered mode. figure 27 contains a block diagram of the arming function operation in unfiltered mode. figure 28 shows the arming output operation under the different spi request conditions. figure 27. arming function block diagram - unfiltered mode x-axis arm condition not present x-axis data latched for arm function and spi sclk mosi miso cs request x-axis request x-axis x-axis response x-axis response request x-axis request x-axis x-axis response arm x-axis response x-axis arm condition not present x-axis arm condition not present x-axis arm condition present t arm pulse stretch time acfg[2] cs axis select arm i/o acfg[1] arming function interpolated sample rate
sensors freescale semiconductor 37 mma685x figure 28. mma685x arming conditions, unfiltered mode 3.8.9.4 arming pulse stretch function a pulse stretch function can be applied to the arming output in moving average mode, or count mode. if the pulse stretch function is not used (aps[ 1:0] = ?00?), the arming ou tput is asserted if and onl y if an arming condition e xists after the most recent evaluated sample. the arming output is de- asserted if and only if an arming condition does not exist afte r the most recent evaluated sample. if the pulse stretch function is used, (aps[1: 0] not equal ?00?), the armi ng output is controlled on ly by the value of the puls e stretch timer value. if the pulse stretch timer value is non-ze ro, the arming output is assert ed. if the pulse stretch timer is zero, the arming output is de-asserted. the puls e stretch counter continuously decrements until it reaches zero. the pulse stretch counter is reset to the programmed pulse stretch value if and onl y if an arming condition exists after the most recent evaluate d sample. reference figure 26 the desired pulse stretch time is programmable for via the aps[1: 0] bits in the armcfg register. exception conditions listed in section 4.5 do not impact prior arming function respons es. if an exception occurs after an arming activation, the corresponding pulse stretch for the existing a rming condition will continue. however, new acceleration reads wi ll not reset the pulse stretch counter r egardless of the acceleration value. x-axis arm condition not present x-axis data latched for arm function and spi sclk mosi miso cs request x-axis request x-axis x-axis response x-axis response request x-axis request x-axis x-axis response arm x-axis response x-axis arm condition not present x-axis arm condition not present x-axis arm condition present t arm_uf_dl t arm_uf_assert
sensors 38 freescale semiconductor mma685x 3.8.9.5 arming pin output structure the arming output pin structure can be set to active high, or ac tive low with the a_cfg bits in the devcfg register as de- scribed in section 3.1.6.5 . the active high and active low pi n output structures are shown in figure 29 . figure 29. arming function - pin output structure 3.8.10 pcm output function mma685x provides the option for a pcm out put function. the pcm output is enabl ed by setting the a_cfg bits in the devcfg register to the appropriate state as described in section 3.1.6.5 . when the pcm function is enabled, the upper 9 bits of the 10-bit, offset cancelled, output scaled acceleration values are used to generate 8 mhz pulse code modulated signals pro- portional to the acceleration onto the pcm pin. a block diagram of the pcm output is shown in figure 30 . exception conditions affect the pcm output as listed in section 4.5 figure 30. pcm output function block diagram arm function arm gating v cc arm function arm gating v cc open drain, active high open drain, active low output scaling oc[9:1] a 9 bit adder arm/pcm b carry sum f clk = 8 mhz sample updated every 8 s 9 9 9 d ff clk q q d ff clk q q d ff clk q q d ff clk q q d ff clk q q d ff clk q q d ff clk q q d ff clk q q d ff clk q q
sensors freescale semiconductor 39 mma685x 3.9 serial peripheral interface mma685x includes a serial peripheral interface (spi) to provide access to the configuration registers and digital data. refer- ence section 4 for details regarding the spi protocol and available commands. 3.10 device initialization following power-up, under-voltage reset, or a spi reset co mmand sequence, mma685x proceeds through an internal initial- ization process as shown in figure 31 . figure 31 also shows the mma685x performance for an example external system level initialization procedure. figure 31. initialization process dly por otp copy to mirror registers offset cancellation startup phase 2 initialize r/w registers to desired state verify offset verify self test & arm asserted offset cancellation startup phase 1 offset cancellation startup phase 3 offset cancellation normal mode ready for spi command endinit clear dly re-initialize r/w registers (if needed) activate self test internal offset error corrected to ?0? deactivate self test normal mode internal initialization external initialization delay deassertion dependent on pulse stretch and/or arming mode assertion dependent on arming mode set endinit read devstat to clear flags re-read devstat to verify status t st_omb t oc_phase1 t oc_phase2 t oc_phase3 t op and st arm notes:1) self test can be enabled and evaluated simultaneously to reduce test time. for failure mode coverage of the arming pins and of potential common axis failures, freescale recommends independent self test activation. t strise 2) t strise and t stfall are dependent on the selected lpf group delay. verify offset & arm deasserted dly
sensors 40 freescale semiconductor mma685x 3.11 overload response 3.11.1 overload performance mma685x is designed to operate within a specified range. acce leration beyond that range (ove rload) impacts the output of the sensor. acceleration beyond the range of the device can gener ate a dc shift at the output of the device that is dependent upon the overload frequency and amplitude. the mma685x g-cell is overdamped, providing the optimal design for overload per- formance. however, the performance of the device during an overlo ad condition is affected by many other parameters, including: ? g-cell damping ? non-linearity ? clipping limits ? symmetry figure 32 shows the g-cell, adc and output cl ipping of mma685x over frequency. the re levant parameters are specified in section 2.1 , and section 2.6 . figure 32. output clipping vs. frequency 3.11.2 sigma delta over range response over range conditions exist when the signal level is beyond t he full-scale range of the devic e but within the computational lim its of the dsp. the ? converter can saturate at levels above those specified in section 2.1 (g adc_clip ). the dsp operates pre- dictably under all cases of over range, although the signal may include residual high frequency components for some time after returning to the normal range of operation due to non-linear effects of the sensor. 5khz f g-cell f lpf g adc_clip g g-cell_clip determined by g-cell 10khz g-cell rolloff acceleration (g) frequency (khz) lpf rolloff r e g i o n c l i p p e d b y g - c e l l r e g i o n c l i p p e d b y a d c r e g i o n o f s i g n a l d i s to r ti o n d u e t o a s y m m e tr y a n d n o n - l i n e a r i ty region of no signal distortion beyond specification region of interest roll-off and adc clipping g range_norm determined by g-cell roll-off and full scale range region clipped by output
sensors freescale semiconductor 41 mma685x 4 spi communications communication with mma685x is complet ed through synchronous serial transfers via spi. mma685x is a slave device con- figured for cpol = 0, cpha = 0, msb first. spi transfers ar e completed through a sequence of two phases. during the first phase, the type of transfer and associated control information is transmitted from the spi master to mma685x. data from mma685x is transmitted during the second phase. any activity on mosi or sclk is ignored w hen cs is negated. consequently, intermediate transfers involving other spi devices may occur between phase one and phase two. refer to figure 33 . figure 33. spi transfer detail t3p1 sclk mosi miso cs t1p1 t2p1 t1p2 t2p2 t3p2 sclk mosi miso cs phase one: command phase two: response phase one: response -previous command
sensors 42 freescale semiconductor mma685x 4.1 spi command format commands are transferred from the spi ma ster to mma685x. valid commands fall in to two categories: register operations, and acceleration data requests. table 26. spi command message summary msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ax a oc 0 0 0 0 0 0 0 0 0 sd arm p command type reference ax= axis selection 0 acceleration data 1n/a a = acceleration data request 0 register operation 1 acceleration data request oc = offset cancelled data request 0 offset cancelled data request 1 raw acceleration data request sd = signed data request signed data request 0 unsigned data request 1 arm = arm function status confirmation disabled / pcm output enabled 0 arming function enabled 1 p = odd parity 0 ax a oc 0 0 0 0 0 0 0 0 0 sd arm p accel data 0010000000000000 oc, signed data, disabled/pcm 0010000000000011 oc, signed data, arm enabled 0010000000000101 oc, unsigned data, disabled/pcm 0010000000000110 oc, unsigned data, arm enabled 0011000000000001 raw, signed data, disabled/pcm 0011000000000010 raw, signed data, arm enabled 0011000000000100 raw, unsigned data, disabled/pcm 0011000000000111 raw, unsigned data, arm enabled 0110000000000001 invalid command 0110000000000010 invalid command 0110000000000100 invalid command 0110000000000111 invalid command 0111000000000000 invalid command 0111000000000011 invalid command 0111000000000101 invalid command 0111000000000110 invalid command p ax a d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 command type reference p00 a4 a3 a2 a1 a0 0 0 0 0 0 0 0 0 register read section 4.4 register address p10 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 register write section 4.4 register address data to be written to register p = odd parity
sensors freescale semiconductor 43 mma685x 4.2 spi response format table 27. spi response message summary msb lsb 1514131211109876543210 cmd a ax response to valid acceleration request data type reference oc 0 ax p s1 s0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 oc = offset cancelled data requested 0 transferred accel data is offset cancelled data 1 transferred accel data is raw data ax = axis requested 0 acceleration data response 1n/a p = odd parity s[1:0] = device status 0 0 in initialization (endinit = ?0?) 0 1 normal data request 1 0 st active, ? /offset over range present 1 1 internal error present / spi error cmd a ax oc 0 ax p s1 s0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data type reference valid accel data request 1 0 oc 0 0 p 0 1 acceleration data accel section 4.3 1 0 oc 0 0 p 1 0 self-test active acceleration data accel 1 0 oc 0 0 p 0 0 acceleration data, initializ ation in process (endinit=?0?) accel 1 1 oc 0 1 p 0 1 invalid accel request n/a 1 1 oc 0 1 p 1 0 invalid accel request n/a 1 1 oc 0 1 p 0 0 invalid accel request n/a msb lsb 1514131211109876543210 cmd a ax response to valid register access data type reference d15 d14 ax p d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 register write 01 0 0 1p1110 d7 d6 d5 d4 d3 d2 d1 d0 register write section 4.4.1 new contents of register register read 00 0 1 0p1110 d7 d6 d5 d4 d3 d2 d1 d0 register read section 4.4.2 contents of register msb lsb 1514131211109876543210 cmd a ax error responses data type reference d15 d14 ax p d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 invalid accel request xx 000p11 sd = 1: 00 0000 0000 sd = 0: 10 0000 0000 register setting mismatch section 4.3 internal error present xx ide bit set (excl. self-test), devinit bit set devres bit set section 4.5.5 miso error xx miso error on previous msg section 4.5.2 spi error x x mosi parity cmd bit 15 = 1 spi timing err spi mismatch err spi protocol errs section 4.5.1 invalid register request 0x 0 0 00111000000000 invalid reg addr, write while endinit set, write to r/o reg section 4.4 self-test error 0x 0 0 1 p 1 1 sd = 1: 00 0000 0000 sd = 0: 10 0000 0000 ide bit set due to self-test error section 4.5.5
sensors 44 freescale semiconductor mma685x 4.3 acceleration data transfers acceleration data requests are initiated when the acceleration bit of the spi command message (a) is set to a logic ?1?. the axis selection bit (ax) and the offs et cancellation selection bit (oc ) of the command message select the type of acceleration data requested, as shown in ta b l e 2 8 to verify that mma685x is configured as expected, each accele ration data request includes the configuration information that impacts the output data. the requested conf iguration is compared against the data pr ogrammed in the writable register array. details are shown in ta b l e 2 9 . acceleration data request commands include a parity bit (p). odd parity is employed. the number of logic ?1? bits in the accel- eration data request command must be an odd number. acceleration data is transmitted on the next spi message if and only if all of the following conditions are met: ? the devinit bit in the d evstat register is not set ? the devres bit in the devstat register is not set ? the ide bit in the devstat register is not set (reference section 4.5.5 ) ? no spi error is detected (reference section 4.5.1 ) ? no miso error is detected (reference section 4.5.2 ) ? no acceleration data request mismat ch failure is detected (reference section 4.5.3.1 ) ? no self-test error is present (reference section 4.5.5.2 ) if the above conditions are met, mma685x responds with a ?v alid acceleration data request? response as shown in table 27 . otherwise, mma685x responds as specified in section 4.5 . 4.4 register access operations two types of register access operations are supported; register write, and register read. regi ster access operations are initi- ated when the acceleration bit (a) of the command message is se t to a logic ?0?. the operation to be performed is indicated by the access selection bit (ax) of the command message. register access operations include a parity bit (p). odd parity is employed. the number of logic ?1? bits in the register acces s operation must be an odd number. table 28. acceleration data request acceleration data request command information data type axis selection bit (ax) offset cancellation select (oc ) 0 0 offset cancelled data 0 1 raw data 1 0 invalid accel request 1 1 invalid accel request table 29. acceleration data re quest configuration information programmable option command message bit writable register information signed or unsigned data sd devcfg[4] (sd ) arming function or pcm output arm devcfg[2 ] || devcfg[1] (a_cfg[2] || a_cfg[1]) access selection bit (ax) operation 0 register read 1 register write
sensors freescale semiconductor 45 mma685x 4.4.1 register write request during a register write request, bits 12 through 8 contain a fi ve-bit address, and bits 7 through 0 contain the data value to b e written. writable registers are defined in ta b l e 3 . the response to a register write operation is shown in ta b l e 2 7 . the response is transmitted on the next spi message if and only if all of the following conditions are met: ? no spi error is detected (reference section 4.5.1 ) ? no miso error is detected (reference section 4.5.2 ) ? the endinit bit is cleared (reference section 3.1.6.2 ) ? this applies to all registers with the exception of the devctl register ? no invalid register request is detected (reference section 4.5.3.2 ) if the above conditions are met, mma685x responds to the register write request as shown in ta b l e 2 7 . otherwise, mma685x responds as specified in section 4.5 . register write operations do not occur inte rnally until the transfer during which they are requested has bee n completed. in the event that a spi error is detected during a register write transfer, the write operation is not completed. 4.4.2 register read request during a register read request, bits 12 th rough 8 contain the five-bit address for the register to be read. bits 7 through 0 mu st be logic ?0?. readable registers are defined in ta b l e 3 . the response to a register read operation is shown in ta b l e 2 7 . the response is transmitted on the next spi message if and only if all of the following conditions are met: ? no spi error is detected (reference section 4.5.1 ) ? no miso error is detected (reference section 4.5.2 ) ? no invalid register request is detected (reference section 4.5.3.2 ) if the above conditions are met, mma685x responds to the register read request as shown in ta b l e 2 7 . otherwise, mma685x responds as specified in section 4.5 . 4.5 exception handling the following sections describe the conditions for each detectab le exception, and the mma685x response for ea ch exception. in the event that multiple exceptions exist, the exce ption response is determined by the priority listed in ta b l e 3 0 . table 30. spi error response priority error priority exception effect on data spi data arming output pcm output 1 spi error error response no update no effect 2 spi miso error error response no update no effect 3 invalid request error response no update no effect 4 devinit bit set error response no update disabled 5 devres error error response no update disabled 6 crc error error response no update no effect 7 self-test error error response no update no effect 8 offset monitor over range no effect no effect no effect 9 ? over range no effect no effect no effect
sensors 46 freescale semiconductor mma685x 4.5.1 spi error the following spi conditions result in a spi error: ? sclk is high when cs is asserted ? the number of sclk rising edges detected while cs is asserted is not equal to 16 ? sclk is high when cs is negated ? command message parity error (mosi) ? bit 15 of acceleration data request is not equal to ?0? ? bits 3 through 11 of an acceleration request are not equal to ?0? ? bits 0 through 7 of a register read request are not equal to ?0? mma685x responds to a spi error with a ?spi error? response as shown in ta b l e 2 7 . this applies to both acceleration data request spi errors, and register access spi errors. the arming function will not be updated if a spi error is detected. the pcm output is not affected by a spi error. 4.5.2 spi data output verification error mma685x includes a function to verify the integrity of the data out put to the miso pin. the function reads the data transmitted on the miso pin and compares it against the data intended to be transmitted. if any one bit doesn?t match, a spi miso mismatch fault is detected and the misoerr flag in the devstat register is set. if a valid spi acceleration request message is received during t he spi transfer with the miso mi smatch failure, the spi accel- eration request message is ignored and mma685x responds wit h a ?miso error? response during the subsequent spi message (reference table 27 ). the arming function is not updated if a miso mismatch failure occurs. th e pcm function is not affected by the miso mismatch failure. if a valid spi register write request message is received during t he spi transfer with the miso mi smatch failure, the register write is completed as requested, but mma685x re sponds with a ?miso error? response as shown in ta b l e 2 7 , during the subse- quent spi message. if a valid spi register read request message is received during th e spi transfer with the miso mi smatch failure, the register read is ignored and mma685x responds with a ?miso error? response as shown in table 27 , during the subsequent spi mes- sage. if the register read request is for the devstat register, the devstat register will not be cleared. in all cases, the misoerr flag in the devstat register will re main set until a successful spi register read request of the devstat register is completed. figure 34. spi data output verification 4.5.3 invalid requests 4.5.3.1 invalid acceleration request the following conditions result in an ?invalid acceleration request? error: ? the axis selection bit (ax) in the command message is set ? the spi ?acceleration data request? command data listed in section 4.3 , ta b l e 2 9 does not match the internal register settings mma685x responds to an ?invalid acceleration request? error with an ?invalid accel request? response as specified in ta b l e 2 7 on the subsequent spi message only. no internal fault is recorded. the arming function will not be updated if an ?ac- celeration data request mismat ch? error is detected. the pcm output is not affected by the ?acceleration data request mis- match? error. register operations will be executed as specified in section 4.4 . d q r d q r dq sclk spi data out shift register data out buffer miso miso err
sensors freescale semiconductor 47 mma685x 4.5.3.2 invalid register request the following conditions result in an ?invalid register request? error: ? an attempt is made to write to an un-writable register (writable registers are defined in section 3.1 , table 3 ). attempts to write to registers $0d, $0f, $11, & $13 will also result in an error. ? an attempt is made to write to a register whil e the endinit bit in the devcfg register is set ? this applies to all registers with the exception of the devctl register ? an attempt is made to read an un-readable register (readable registers are defined in section 3.1 , ta b l e 3 ). attempts to read registers $07, $0d, $0f, $11, & $13 will also result in an error. mma685x responds to an invalid register request? error wit h an ?invalid register request? response as shown in table 27 . 4.5.4 device reset indications if the devinit, or devres bit is set in the devstat register as described in section 3.1.10 , mma685x will respond to ac- celeration data requests with an ?internal e rror present? response until the bits are cleared in the devstat register. the devi nit bit is cleared automatically when device initialization is complete (reference t op in section 2.6 ). the devres bit is cleared on a read of the devstat register. the arming function will not be upd ated on acceleration data request commands if the devinit or devres bit is set in the devstat re gister. the pcm output is disabled if the devini t or devres bit is set. 4.5.5 internal error the following errors will result in an internal error, and set the ide bit in the devstat register: ? otp crc failure ? writable register crc failure ? self-test error ? invalid internal logic states 4.5.5.1 crc error if the ide bit is set in the devstat register due to an otp sh adow register or writable register crc failure as described in section 3.2 , mma685x will respond to acceleration data requests with an ?internal error present? response until the ide bit is cleared in the devstat register. the arming function will no t be updated on acceleration data request commands if a crc error is detected. the pcm output is not affected by the crc error. if the crc error is in the writable register array, and the endi nit bit in the devcfg register has been set, the error can only be cleared by a device reset. the ide bit will not be cleared on a read of the devstat register. if the crc error is in the otp shadow register array, the error cannot be cleared. register operations will be executed as specified in section 4.4 . 4.5.5.2 self-test error if the ide bit is set in the devstat register due to a self-test activation failure, mma685x will respond to acceleration data requests with a ?self-test error? response until the ide bit is cleared in the devstat register. the arming function will not b e updated on acceleration data request commands if a self-test er ror is detected. the pcm output is not affected by the self- test error. the ide bit in the devstat register will remain set until a read of the devstat regist er occurs, even if the intern al failure is removed. if the internal error is still present wh en the devstat register is read, the ide bit will remain set. register operations will be executed as specified in section 4.4 . 4.5.6 offset monitor over range if an offset monitor over range is present as described in section 3.8.5 , mma685x will respond to an acceleration request with a ?valid acceleration data request? response, but the status bits (s[1:0]) will be set to ?10?. the arming function will be upd ated on acceleration data request commands even if an offset moni tor over range is detected. once the over range condition is removed, mma685x will respond to acceleration requests with a ?val id acceleration data request? response with the status bits (s[1:0]) set to ?10? on the next spi transfer, and a ?valid acce leration data request? response with normal status on subsequen t spi transfers. the off bit in the devstat register will remain set until a read of the devstat register occurs. the pcm output is not affected by t he offset monitor over range condition. register operations will be executed as specified in section 4.4 .
sensors 48 freescale semiconductor mma685x 4.5.7 ? over range if a ? over range failure is present as described in section 3.11.2 , mma685x will respond to acceleration data requests with a ?valid acceleration data request? response, but the status bits (s[1:0]) will be set to ?10?. the arming function will be upd ated on acceleration data request commands even if a ? over range is detected. once the over range condition is removed, mma685x will respond to acceleration requests with a ?valid accele ration data request? response with the status bits (s[1:0]) set to ?10? on the next spi transfer, and a ?valid accelerati on data request? response with normal status on subsequent spi transfers. the sdov bit in the devstat register will rema in set until a read of the devstat register occurs. the pcm output is not affected by the ? over range condition. register operations will be executed as specified in section 4.4 . 4.6 initialization spi response the first data transmitted by mma685x following reset is the spi error response shown in table 27 . this ensures that an un- expected reset will always be detectable. mma685x will respond to al l acceleration data requests with the ?invalid acceleration data request? response until th e devres bit in the devstat register is cleare d via a read of the devstat register. the arming function will not be updated on acceleration data request comman ds until the devres bit in the devstat register is cleared. 4.7 acceleration data representation acceleration values are determined from the 10-bit digital output (dv) using the following equations: the linear range of digital values for signed data is -480 to +480, and for unsigned data is 32 to 992. resulting ranges and some nominal acceleration values are shown in table 31 . acceleration sensitivity lsb dv 512 ? () = acceleration sensitivity lsb dv = for signed data for unsigned data table 31. nominal acceleration data values unsigned digital value signed digital value nominal acceleration trimmed for maximum sensitivity (g) trimmed for maximum range (g) 993 - 1023 481 - 511 unused 992 480 19.666 117.19 991 479 19.625 116.94 2 2 2 2 2 2 2 2 2 2 2 2 514 2 +0.082 +0.488 513 1 +0.041 +0.244 512 0 0 0 511 -1 -0.041 -0.244 510 -2 -0.082 -0.488 2 2 2 2 2 2 2 2 2 2 2 2 33 -479 -19.625 -116.94 32 -480 -19.666 -117.19 1 - 31 -481 to -511 unused 0 -512 fault
sensors freescale semiconductor 49 mma685x figure 35 shows the how the possible output data codes are determin ed from the input data and the error sources. the rele- vant parameters are specified in section 2.4 . figure 35. mma685x acceleration data output vs. acceleration input
sensors 50 freescale semiconductor mma685x package dimensions case 1477-02 issue b 16 lead qfn page 1 of 3
sensors freescale semiconductor 51 mma685x package dimensions case 1477-02 issue b 16 lead qfn page 2 of 3
sensors 52 freescale semiconductor mma685x package dimensions case 1477-02 issue b 16 lead qfn page 3 of 3
mma685x rev. 1 05/2010 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale and the freescale logo are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2010. all rights reserved. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http:/www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor lite rature distribution center 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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